About Hardware Description Languages for PLIS Design course
This course can also be credited toward ECEA 5361 in CU Boulder's Electrical Engineering Master of Science program. Hardware Description Languages for Logic Design allows students to design circuits using VHDL and Verilog, the most common design methods for FPGAs. It uses natural learning processes to make learning the languages easy. Simple examples are presented first, then the language rules and syntax, followed by more complex examples, and finally the use of bench simulations to verify the correctness of the designs. Lecture presentations are supported by a large number of programming example problems to build proficiency in the languages. Upon completion of the course, each student will have a fundamental knowledge of both languages, and, more importantly, enough knowledge to continue studying and gaining experience in Verilog and VHDL on their own.
